Data storage systems which use removable media and typically record mass data, such as tape drives and optical disks, rely on strong error-correcting codes (ECC). Tape drives and CD devices employ powerful and complexity-efficient ECC, which is based on code concatenation of an outer C2-code and an inner C1-code. The product code specified in the Linear Tape-Open, Generation 3 (LTO-3) standard is a particular instance of a concatenated coding scheme where both the inner and outer codes are RS-based codes of length 480 and 64, respectively as presented in TABLE I.
TABLE ILTO-3 product code012. . .465466467468. . .479 0012. . .456466467 1468469470. . .933934935C1.Parity.Bytes.5253248042480524806. . .25269252702527154C2 Parity Bytes...63
A subdata set is a 64×480 array of bytes, i.e., it contains 30,720 bytes, with 54×468=25,272 data bytes, resulting in a code rate of 0.8227. Each 480-byte row comprises a codeword pair. More specifically, the outer C2-code is an [N2=64, K2=54, d2=11] RS code over the Galois field GF(256), where N2 denotes the length, K2 the dimension, and d2 the minimum Hamming distance of the code. The inner C1-code is obtained by even/odd interleaving of an [240, 234, 7] Reed-Solomon (RS) code over GF(256).
In magnetic and optical recording, modulation codes are used to enable timing recovery from the read-back signal and to allow for short path memories in the detector without substantial performance loss. Thus, in the write path prior to writing ECC encoded data onto the media, the ECC encoded data is passed through a modulation encoder. Referring to FIG. 1, a method by which the user data is first encoded by ECC 102 and then passed through a modulation encoder 104, such as a 16/17 run length limited (RLL) encoder, is known as a forward concatenation (FC) architecture 100. To improve ECC performance, there is a long block interleaver 106 in the LTO-3 write path, denoted as the Interleaving & Track Assignment block. This block 106 buffers 64 consecutive product subdata sets thereby accumulating a total of 64×64=4096 rows. These 4096 rows are assigned to the 16 tracks 108 of the tape media in a predefined order. For each track there is a rate-16/17 modulation encoder, which encodes the assigned rows and guarantees the predetermined modulation constraints, namely, a global G=13 and an interleaved I=11 constraint.
Recently, reverse concatenation (RC) architectures have received increased attention in the hard disk drive (HDD) industry. FIG. 2 is a block diagram of such an architecture 200. In an RC architecture 200, the order of the ECC-encoder and modulation encoder is reversed such that the data is first passed through a modulation encoder 202 and the modulated data is ECC-encoded using a systematic encoder 204 for the error correcting code. The ECC parity symbols are either encoded using a second modulation encoder 206, as illustrated, or they are inserted into the data symbol stream at the bit level or symbol level. Inserting entire parity symbols into the data symbol stream is referred to as partial symbol interleaving. Parity insertion strategies result in simple schemes with no error propagation; however, such strategies may weaken the original modulation constraints. Nonetheless, there are three major benefits which make RC attractive:                a) There is no error propagation through the modulation decoder.        b) Because error propagation is not an issue, the first modulation code can be taken to be very long, allowing the use of capacity-efficient and high-rate modulation codes, and thereby resulting in code rate gains.        c) In the read-back path, the ECC decoding block is located immediately after the channel detection block, which enables soft information to be passed from the detector to the decoder on a bit-by-bit basis. This creates the appropriate framework for using novel ECC techniques, which are based on turbo and LDPC codes and which hold the promise of large performance improvements. Furthermore, in this framework, parity post-processing schemes can easily be implemented.        
It would be desirable for the same benefits to also be provided in the framework of tape recording. However, the ECC used in HDDs has a different structure than the ECC used in tape recording. In HDDs, ECC is essentially based on a single high-rate Reed-Solomon (RS) code whereas in tape, large powerful product codes are used which require a new RC architecture. RC has been proposed for 1-dimensional ECC architectures, where the ECC typically consists of a single code such as a Reed-Solomon code or an LDPC code. However, the known RC schemes have not addressed the particular issues which arise from ECC which is based on concatenated or product codes. With a concatenated or product code, the output of the inner C1 code is mapped to the tracks/channels and, thus, all rows should satisfy a predetermined modulation constraint. Therefore, a significant drawback is presented, which is illustrated with respect to the LTO-3 product code. Referring again to TABLE I, putting the modulation encoder prior to a systematic ECC encoder will result in only K2 rows which meet the modulation constraint except for the C1-parity part. The remaining N2−K2 rows (rows 54-63), which consist of C2-parity bytes, do not meet the modulation constraint. The C1-parity part poses a minor problem because it can be treated separately, as in the case of 1-dimensional ECC. However, for the C2-parity part no efficient solution has yet been proposed. Thus, a substantial number of rows would not satisfy a modulation constraint and would need further processing. Following a 1-dimensional RC strategy, these rows would need to be passed through a second modulation encoder or be dealt with using a parity insertion strategy. Both techniques would result in undesired features: a) a second modulation code would lead to error propagation and does not allow soft-information to be passed from the channel detector to the ECC decoder on a bit-by-bit basis; and b) partial symbol interleaving would result in poor performance in case of a dead track because entire faulty rows would be subdivided and spread into other rows causing many errors in many rows.
The aforementioned mentioned drawbacks might be avoided if the outer C2-encoder would commute with the first modulation encoder: that is, if the order of encoding would not matter. But this is not the case and to date a reverse concatenation architecture has not been proposed for product codes.